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400mA SmartLDO MOSFET
January 3, 2000
TM
with Internal Pass
SC1532
TEL:805-498-2111 FAX:805-498-3804 WEB:http://www.semtech.com
DESCRIPTION
Intended for applications such as Power Managed PCI, the SC1532 is designed to maintain a glitch-free 3.3V output when at least one of two inputs, 5V (VIN1) and 3.3V (VIN2), is present. The SC1532 combines a 5V to 3.3V linear regulator with an integral 3.3V bypass switch, along with logic and detection circuitry to control which supply provides the power for the output. Whenever VIN1 exceeds a predetermined threshold value, the internal 3.3V PMOS linear regulator is enabled, and the internal pass NMOS is turned off. When VIN1 falls below a lower threshold value, the NMOS pass device is turned on and the PMOS linear regulator is turned off. This ensures an uninterrupted 3.3V output even if VIN1 falls out of specification. When both supplies are simultaneously available, the PMOS linear regulator will be turned on, and the NMOS pass will be turned off, thus preferentially supplying the output from the 5V supply. The internal 5V detector has its upper threshold (for VIN1 rising) set to 4.18V (typical) while the lower threshold (for VIN falling) is at 4.1V (typical) giving a hysteresis of approximately 80mV. The SC1532 is available in the popular SO-8 surface mount package.
FEATURES * Glitch-free transition between input sources * Internal logic selects input source * 5V detector with hysteresis * 1% regulated output voltage accuracy * 400mA load current capability APPLICATIONS * Desktop Computers * Network Interface Cards (NICs) * PCMCIA/PCI Interface Cards * Peripheral Cards ORDERING INFORMATION
Part Number SC1532CS
(1)
Package SO-8
Note: (1) Add suffix `TR' for tape and reel packaging.
TYPICAL APPLICATION CIRCUIT
3.3VAUX IN 5V IN 3.3V OUT 1 2 3 4
U1 VIN2 VIN1 VO CP GND GND GND GND 8 7 6 5
SC1532 C1 4.7uF C2 4.7uF C3 4.7uF C4 1nF
NOTES: (1) Ceramic capacitors are recommended - see Applications Information for further details. (2) Output capacitor C3 needs to be 1.0uF or greater for stability. Additional capacitance (tantalum or ceramic) will improve overall performance.
1 (c) 2000 SEMTECH CORP. 652 MITCHELL ROAD NEWBURY PARK CA 91320
400mA SmartLDO MOSFET
January 3, 2000
TM
with Internal Pass
SC1532
ABSOLUTE MAXIMUM RATINGS
Parameter Input Supply Voltages Charge Pump Capacitor Pin Voltage Output Current Operating Ambient Temperature Range Operating Junction Temperature Range Storage Temperature Range Lead Temperature (Soldering) 10 Sec Thermal Impedance Junction to Ambient ESD Rating (Human Body Model) NOTE: (1) 1 inch square of 1/16" FR-4, double sided, 1 oz. minimum copper weight.
(1)
Symbol VIN1, VIN2 CP IO TA TJ TSTG TLEAD JA ESD
Maximum -0.5 to +7 -0.5 to +16 400 -5 to +70 -5 to +125 -65 to +150 300 65 4
Units V V mA C C C C C/W kV
ELECTRICAL CHARACTERISTICS
Unless specified, TA = 25C, VIN1 = 5V, VIN2 = 3.3V, IO = 400mA, CIN1 = 4.7uF, CIN2 = 4.7uF, CO = 4.7uF, Cp=1nF. Values in bold apply over full operating temperature range.
Parameter VIN1 Supply Voltage Quiescent Current
(1)
Symbol
Test Conditions
MIN
TYP MAX Units
VIN1 IQ1
VIN2 = 0V VIN1 = 5V, 0V VIN2 3.6V, IO = 0mA
4.3
5.0 2.0
5.5 3.0 4.0
V mA
Reverse Leakage From VIN2 VIN2 Supply Voltage Quiescent Current
IVIN1 VIN2 IQ2
VIN1 = 0V, VIN2 = 3.6V, IO = 0mA 3.0 VIN2 = 3.3V, 0V VIN1 5.5V, IO = 0mA
0
1
A
3.3
3.6
V A
650 1300 2000
Reverse Leakage From VIN1 5V Detect
(1)(2)
(1)
IVIN2 VTH(LO) VHYST VTH(HI)
VIN1 = 5.5V, VIN2 = 0V, IO = 0mA VIN1 Falling, IO = 20mA IO = 20mA VIN1 Rising, IO = 20mA
0
1
A
Low Threshold Voltage Hysteresis High Threshold Voltage
3.90 60
4.10 80 4.18 150 4.30
V mV V
2 (c) 2000 SEMTECH CORP. 652 MITCHELL ROAD NEWBURY PARK CA 91320
400mA SmartLDO MOSFET
January 3, 2000
TM
with Internal Pass
SC1532
ELECTRICAL CHARACTERISTICS (Cont.)
Unless specified, TA = 25C, VIN1 = 5V, VIN2 = 3.3V, IO = 400mA, CIN1 = 4.7uF, CIN2 = 4.7uF, CO = 4.7uF, Cp=1nF. Values in bold apply over full operating temperature range.
Parameter VO LDO Voltage Accuracy
Symbol
Test Conditions
MIN
TYP MAX Units
VO
IO = 20mA 4.3V VIN1 5.5V, 0mA IO 400mA 3.90V VIN1 4.3V, VIN2 = 3.3V, (1) 0mA IO 400mA
(1)
-1 -2 3.000 360
+1 +2
%
V 500 m
VIN2 Pass Device On Resistance (Aux. NMOS) Line Regulation
(1)(3)
RDS(ON)
VIN1 < 3.9V, 0mA IO 400mA
REG(LINE) REG(LOAD)
VIN1 = 4.3V to 5.5V
0.3
0.6 0.7
%
Load Regulation
IO = 20mA to 400mA
0.3
0.6 0.7
%
Current Limit (LDO) Output Current ILIM VIN1 = 5V, VIN2 = 0V, VO = 0V 600 975 1200 1400 Over Temperature Protection High Trip Level Hysteresis THI THYS VIN1=5V VIN1=5V 175 10 C C mA
NOTES: (1) Guaranteed by design. (2) Recommended source impedance for 5V supply: 0.125. This will ensure clean transitions between supplies with no "chattering" (see Applications Information). (3) Refer to block diagram.
3 (c) 2000 SEMTECH CORP. 652 MITCHELL ROAD NEWBURY PARK CA 91320
400mA SmartLDO MOSFET
January 3, 2000
TM
with Internal Pass
SC1532
BLOCK DIAGRAM
PIN CONFIGURATION
Top View
(SO-8)
PIN DESCRIPTIONS
Pin 1 2 3 4 5 6 7 8 Pin Name VIN2 VIN1 VO CP GND GND GND GND Pin Function Secondary input supply, nominally 3.3V. Main input supply for the IC, nominally 5V. 3.3V out. Charge pump capacitor connection. Ground pin. Ground pin. Ground pin. Ground pin.
4 (c) 2000 SEMTECH CORP. 652 MITCHELL ROAD NEWBURY PARK CA 91320
400mA SmartLDO MOSFET
January 3, 2000
TM
with Internal Pass
SC1532
TYPICAL CHARACTERISTICS
Quiescent Current (IQ1) vs. Junction Temperature vs. VIN2
2.0 VIN2 = 3.6V 1.8 1.6 600 1.4 IQ1 (mA) VIN2 = 0V 1.0 0.8 0.6 200 0.4 0.2 0.0 -25 0 25 50 TJ (C) 75 100 125 VIN1 = 5V IO = 0mA 100 0 -25 0 25 50 TJ (C) 75 100 125 VIN2 = 3.3V IO = 0mA IQ2 (A) 1.2 500 400 300 VIN1 = 5.5V 700 800 VIN1 = 0V
Quiescent Current (IQ2) vs. Junction Temperature vs. VIN1
LDO Output Voltage vs. Junction Temperature vs. Output Current
3.310 3.305 3.300 3.295 VO (V) 3.290 3.285 3.280 3.275 3.270 -25 0 25 50 TJ (C) 75 100 125 IO = 400mA REG(LINE) (%) IO = 200mA VIN1 = 5V VIN2 = 3.3V IO = 0mA 0.30 0.25 0.20 0.15 0.10 0.05 0.00 -25 0 0.40 0.35
LDO Line Regulation vs. Junction Temperature
VIN1 = 4.3V to 5.5V IO = 400mA
25
50 TJ (C)
75
100
125
LDO Load Regulation vs. Junction Temperature
0.40 0.35 0.30 REG(LOAD) (%) ILIM (mA) 0.25 0.20 0.15 0.10 0.05 0.00 -25 0 25 50 TJ (C) 75 100 125 200 0 -25 0 800 600 400 VIN1 = 5V VIN2 = 3.3V IO = 20mA to 400mA 1200 1000
LDO Current Limit vs. Junction Temperature
VIN1 = 5V VIN2 = 0V VO = 0V
25
50 TJ (C)
75
100
125
5 (c) 2000 SEMTECH CORP. 652 MITCHELL ROAD NEWBURY PARK CA 91320
400mA SmartLDO MOSFET
January 3, 2000
TM
with Internal Pass
SC1532
TYPICAL CHARACTERISTICS (Cont.)
VIN2 Pass Device On Resistance vs. Junction Temperature
500 450 400 350 RDS(ON) (m) VTH (V) 300 250 200 150 4.00 100 50 0 -25 0 25 50 TJ (C) 75 100 125 3.95 3.90 -25 0 25 50 TJ (C)
(1)(2)
5V Detect Threshold Voltage vs. Junction Temperature
4.30 4.25 4.20 4.15 4.10 VTH(LO) 4.05 VIN2 = 3.3V IO = 20mA VTH(HI)
VIN1 = 0V VIN2 = 3.3V IO = 400mA
75
100
125
VO(MIN) With VIN1 Rising
VO(MIN) With VIN1 Falling
(1)(2)
Trace 1: VO, offset 3.3V, 100mV/div. Trace 2: VIN1 rising through VTH(HI), 2V/div. VO(MIN) = 3.11V NOTES: (1) In Application Circuit on page 1. (2) RL = 8.2.
Trace 1: VO, offset 3.3V, 100mV/div. Trace 2: VIN1 falling through VTH(LO), 2V/div. VO(MIN) = 3.05V
6 (c) 2000 SEMTECH CORP. 652 MITCHELL ROAD NEWBURY PARK CA 91320
400mA SmartLDO MOSFET
January 3, 2000
TM
with Internal Pass
SC1532
TYPICAL CHARACTERISTICS (Cont.)
Transient Load Response
(1)
Trace 1: VO, offset 3.3V, 50mV/div. Trace 2: IO stepping from 0mA to 400mA NOTES: (1) In Application Circuit on page 2.
APPLICATIONS INFORMATION
Introduction The SC1532 is intended for applications such as power managed PCI and network interface cards (NICs), where operation from a 3.3V VAUX supply may be required when the 5V supply has been shut down. It provides a simple, low cost solution that uses very little pcb real estate. During regular operation, 3.3V power for the PCI card is provided by the SC1532's on-board low dropout regulator, generated from the 5V supply. When the 5V supply is removed and 3.3V VAUX is available, the SC1532 connects this supply directly to its output using an internal NMOS pass device. Component Selection Output capacitors - Semtech recommends a 4.7F or greater ceramic capacitor at the output for the best combination of performance and cost effectiveness. Increasing the capacitance value improves transient response and glitch performance. The SC1532 is very tolerant of output capacitor value and ESR variations, in fact any combination of capacitors with C 1F and ESR < 1 is sufficient for stability. This target is easily met using surface mount ceramic or tantalum capacitors.
Input capacitors - Semtech recommends the use of a 4.7F ceramic capacitor at both inputs. This allows for the device being some distance from any bulk capacitance on the rail. Additionally, input droop due to load transients is reduced, improving load transient response and aiding smooth supply transitions. Tantalum capacitors should not be used. Charge pump capacitor - Semtech recommends the use of a 1nF ceramic capacitor between CP and GND. Thermal Considerations When operating from the 5V supply, the power dissipation in the SC1532 is approximately equal to the product of the output current and the input to output voltage differential:
PD (VIN 1 - VO ) * I O
The absolute worst-case dissipation is given by:
PD ( MAX ) = (VIN1( MAX ) - VO ( MIN ) )* IO ( MAX ) + VIN1( MAX ) * IQ1( MAX ) + VIN 2 ( MAX ) * IQ 2 ( MAX )
Note that the VIN2(MAX) x IQ2(MAX) term does not apply if VIN2 is not supplied.
7 (c) 2000 SEMTECH CORP. 652 MITCHELL ROAD NEWBURY PARK CA 91320
400mA SmartLDO MOSFET
January 3, 2000
TM
with Internal Pass
SC1532
APPLICATIONS INFORMATION (Cont.)
Inserting VIN1 = 5.5V, VO = 3.234V, IO = 400mA, VIN2 = 3.6V, IQ1 = 4mA and IQ2 = 2mA yields:
PD ( MAX ) = 0 . 936 W
In general, this can be avoided by minimizing supply trace lengths and resistances. In circumstances where the source impedance is causing supply "chattering", increasing the value of the VIN1 input capacitor should solve the problem by reducing the instantaneous drop or jump in VIN1 as the supplies are switched. Layout Considerations While layout for linear devices is generally not as critical as for a switching application, careful attention to detail will ensure reliable operation. See Figure 1 below for a sample layout. 1) Attaching the part (pins 5 to 8) to a larger copper footprint will enable better heat transfer from the device, especially on PCBs where there are internal ground and power planes. 2) Place the input and output capacitors close to the device for optimal transient response.
Using this figure, we can calculate the maximum thermal impedance allowable to maintain TJ 125C at an ambient temperature of 55C:
R TH ( J - A )( MAX )
(T =
J( MAX )
- TA ( MAX ) )
PD ( MAX )
=
(125 - 55 ) = 75 C / W
0 .936
This is readily achievable using pcb copper area to aid in conducting the heat away from the device (see Figure 1 below). VIN1 Source Impedance In order to ensure seamless transitions between supplies with VIN1 rising and falling, it is recommended that the source impedance of VIN1 is less than 0.125. This is because as the output current switches from VIN1 to VIN2 and visa-versa, the supplies can "chatter" if:
I O * R SOURCE > VHYST
Top Copper
Top Silk Screen
Fig. 1: Suggested pcb layout based upon Application Circuit on Page 1. NOTES: (1) All vias go to ground plane. (2) Copper area on pins 5 thru 8 is recommended, 0.5" x 0.5" area only is shown. Connect to the ground plane with a via or vias.
8 (c) 2000 SEMTECH CORP. 652 MITCHELL ROAD NEWBURY PARK CA 91320
400mA SmartLDO MOSFET
January 3, 2000
TM
with Internal Pass
SC1532
OUTLINE DRAWING - SO-8
JEDEC REF: MS-012AA
MINIMUM LAND PATTERN - SO-8
ECN99-789
9 (c) 2000 SEMTECH CORP. 652 MITCHELL ROAD NEWBURY PARK CA 91320

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